A Low-Power ADPLL with Calibration-Free RO-Based Injection-Locking TDC for BLE Applications

This paper proposes a low-power all-digital phase-locked loop (ADPLL) with calibration-free ring oscillator (RO)-based injection-locking time to digital converter (TDC) for BLE applications. The RO is reused as the delay cell of TDC, and quantization step TDC always tracked period; hence no calibration needed in this architecture. We adopt tuning lower bandwidth so decrease power consumption injection current. Moreover, fractional part phase error detection turned down coarse ADPLL save power. An LC-based digital-controlled (LCDCO) 6.4 nH inductor resistive bias used have low better noise performance. fabricated 40 nm CMOS 1 V supply consumes 1.4 mW when it locked. measured −114 dBc/Hz at MHz offset. test results show significant saving. Thus, can be promising candidate